In the design of data processing systems, the designer must choose to make the entire system synchronous, asynchronous, or have a synchronous bus portion and an asynchronous or bus portion. Most systems are made synchronous whereby every component in the system operates from a single clock or system of integrated clocks. The major advantage of a synchronous configuration is that the various components in the system can query and respond to each other in a high speed, high performance fashion.
In asynchronous bus architecture, the various components in the data processing system each operate with their own local clock, not necessarily synchronized to any other clock in the system. In these configurations, some components, too slow or too fast to operate in a synchronous system, can be used. In general, the major advantage of an asynchronous bus system is the flexibility in the number and kind of components that can be placed into the system. However, such systems incur a time penalty since the interchange of information between components involves a delay in acting upon the received information by the receiving component until the received information signals are synchronized to the local clock.
Even though synchronous and asynchronous systems are different in concept and use, the inventors herein observed that the difference between the two systems in terms of memory controller circuits can be made small. In the case of an asynchronous system, controller interface circuits are needed to synchronize the received signals to the internal local clock whereas in the synchronous case, the received signals are already synchronous with the clock. In each case, however, once the data is synchronized to the local clock, the rest of the operations are essentially the same. From this observation, the inventors herein have developed a memory controller with interface circuits that can be used for the highly flexible asynchronous case and can also be used in a high performance synchronous network if desired. Since the same memory controller can be used for both cases, a universal memory controller is provided thereby obviating the need for designing a multiplicity of memory controllers and avoiding the stocking of additional parts.
IBM Technical Disclosure Bulletin, March 1977, pages 3643 et seq. discloses a bus system which can address either a synchronous memory or an asynchronous memory. However, the controllers for each memory are different and therefore a universal memory controller is not described.
U.S. Pat. No. 3,999,163 discloses a system which is connected to several different memory devices, tapes, disks, etc., some of which are said to be synchronous and some of which are said to be asynchronous. The memory controller, however, is connected over only a synchronous bus to the CPU.